Here is the current repository for the Rewriting Logic Semantics (RLS) of Verilog. This is an executable semantics that may be used both as a Verilog simulator and a tool for exploring the inherent concurrency of Verilog designs. Reading the semantics can also lead to a deeper understanding of Verilog, as presented in the IEEE 1364 standard.
The directory contains several files.
- bitvector.maude - this is code to handle the representation of bitvectors. While necessary for the definition to work correctly, we do not view this as part of the definition
- k.maude - this has some generic definitions that we add-in to any language definition that uses the continuations-based RLS style.
- string-format.maude - this provides support for the IO statements in Verilog. It can be likened to a more general sprintf from the C library. This is also not really part of the Verilog definition.
- verilog-syntax.maude - this is the definition of the syntax of Verilog. It is very close to actual Verilog syntax. The biggest difference is maude requires spacing around certain tokens (such as semicolon). Verilog identifiers must be declared as operators of sort Name. Lastly, we do not support sized integer literals like in Verilog. Strings and integers must be placed in the operators s() and i() respectively. For examples of writing Verilog programs using this slightly modified syntax, look at test.maude (described below).
- deterministic-continuous-assigment-semanitcs.maude - this is the version of the Verilog semantics with deterministic continuous assignments that only allow one outstanding update event.
- nondeterministic-continuous-assignment-semantics.maude - this is the version of the semantics where continuous net assignments are converted to always blocks with blocking assignments.
- test.maude - this contains some tests. Currently, it is setup to use the deterministic continuous assignment semantics. This can be modified by changing the load statement at the top of the file.