BusMOP

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Special:LogicRepository3MOP LogicRepository

FSM

ERE

CFG

PTLTL

LTL

PTCaRet

SRS

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JavaMOP

JavaFSM

JavaERE

JavaCFG

JavaPTLTL

JavaLTL

JavaPTCaRet

JavaSRS

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BusMOP

BusFSM

BusERE

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BusPTLTL

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Brief Discription

BusMOP is an extension of MOP designed to monitor system buses using FPGA-based monitors. More information can be found in:


Hardware Runtime Monitoring for Dependable COTS-based Real-Time Embedded Systems 
Rodolfo Pellizzoni, Patrick Meredith, Marco Caccamo and Grigore Rosu
RTSS'08, IEEE, pp. 481-491. 2008
PDF, Experiments, Slides(PPTX), IEEE, RTSS'08, BIB


Note: The syntax of handlers and declarations has changed since the publication to be more consistent with JavaMOP.


Funding

This work was supported in part by NSF grant CNS-0720512. Any opinions, findings, and conclusions or recommendations expressed in this web-site are those of the authors and do not necessarily reflect the views of the NSF.

Online Trial

We have an online interactive webpage for the two logics we currently support, extended regular expressions (ERE) and past time temporal logic (PTLTL). Examples of each are in their particular directories. For help with specification syntax click the Specification Syntax Help button.

Note: if there are any technical difficulties please alert pmeredit@cs.uiuc.edu

Choose an example:
  • ERE
    • InterruptFix
    • SafeConversionSpeed
    • SafeCounterModify
  • FSM
    • InterruptFix
    • NoDisableWhileConverting
    • SafeConversionSpeed
    • SafeCounterModify
    • SafeDivrModify
  • PTLTL
    • NoDisableWhileConverting
    • SafeDivrModify
 

Please press the Run button once and wait; it may take a few seconds to run BusMOPOnline; the execution of BusMOPOnline using this web interface is limited to 2 minutes of CPU time and 500 MB of RAM.

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